# //  Questa Sim
# //  Version 10.7b_1 linux Jul 26 2018
# //
# //  Copyright 1991-2018 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# do fft_sim_run_msim_rtl_verilog.do
# if ![file isdirectory fft_sim_iputf_libs] {
# 	file mkdir fft_sim_iputf_libs
# }
# 
# if ![file isdirectory verilog_libs] {
# 	file mkdir verilog_libs
# }
# 
# vlib verilog_libs/altera_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_ver".
# vmap altera_ver ./verilog_libs/altera_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap altera_ver ./verilog_libs/altera_ver 
# Copying /tools/mentor/questa_10.7b_1/questasim/linux/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# vlog -vlog01compat -work altera_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/altera_primitives.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:03 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work altera_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/altera_primitives.v 
# -- Compiling module global
# -- Compiling module carry
# -- Compiling module cascade
# -- Compiling module carry_sum
# -- Compiling module exp
# -- Compiling module soft
# -- Compiling module opndrn
# -- Compiling module row_global
# -- Compiling module TRI
# -- Compiling module lut_input
# -- Compiling module lut_output
# -- Compiling module latch
# -- Compiling module dlatch
# -- Compiling module prim_gdff
# -- Compiling module dff
# -- Compiling module dffe
# -- Compiling module dffea
# -- Compiling module dffeas
# -- Compiling module dffeas_pr
# -- Compiling module prim_gtff
# -- Compiling module tff
# -- Compiling module tffe
# -- Compiling module prim_gjkff
# -- Compiling module jkff
# -- Compiling module jkffe
# -- Compiling module prim_gsrff
# -- Compiling module srff
# -- Compiling module srffe
# -- Compiling module clklock
# -- Compiling module alt_inbuf
# -- Compiling module alt_outbuf
# -- Compiling module alt_outbuf_tri
# -- Compiling module alt_iobuf
# -- Compiling module alt_inbuf_diff
# -- Compiling module alt_outbuf_diff
# -- Compiling module alt_outbuf_tri_diff
# -- Compiling module alt_iobuf_diff
# -- Compiling module alt_bidir_diff
# -- Compiling module alt_bidir_buf
# -- Compiling UDP PRIM_GDFF_LOW
# -- Compiling UDP PRIM_GDFF_LOW_SCLR_PRIORITY
# -- Compiling UDP PRIM_GDFF_HIGH
# -- Compiling UDP PRIM_GDFF_HIGH_SCLR_PRIORITY
# 
# Top level modules:
# 	global
# 	carry
# 	cascade
# 	carry_sum
# 	exp
# 	soft
# 	opndrn
# 	row_global
# 	TRI
# 	lut_input
# 	lut_output
# 	latch
# 	dlatch
# 	dff
# 	dffe
# 	dffea
# 	dffeas
# 	dffeas_pr
# 	tff
# 	tffe
# 	jkff
# 	jkffe
# 	srff
# 	srffe
# 	clklock
# 	alt_inbuf
# 	alt_outbuf
# 	alt_outbuf_tri
# 	alt_iobuf
# 	alt_inbuf_diff
# 	alt_outbuf_diff
# 	alt_outbuf_tri_diff
# 	alt_iobuf_diff
# 	alt_bidir_diff
# 	alt_bidir_buf
# End time: 09:28:03 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlib verilog_libs/lpm_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/lpm_ver".
# vmap lpm_ver ./verilog_libs/lpm_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap lpm_ver ./verilog_libs/lpm_ver 
# Modifying modelsim.ini
# vlog -vlog01compat -work lpm_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/220model.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:03 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work lpm_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/220model.v 
# -- Compiling module LPM_MEMORY_INITIALIZATION
# -- Compiling module LPM_HINT_EVALUATION
# -- Compiling module LPM_DEVICE_FAMILIES
# -- Compiling module lpm_constant
# -- Compiling module lpm_inv
# -- Compiling module lpm_and
# -- Compiling module lpm_or
# -- Compiling module lpm_xor
# -- Compiling module lpm_bustri
# -- Compiling module lpm_mux
# -- Compiling module lpm_decode
# -- Compiling module lpm_clshift
# -- Compiling module lpm_add_sub
# -- Compiling module lpm_compare
# -- Compiling module lpm_mult
# -- Compiling module lpm_divide
# -- Compiling module lpm_abs
# -- Compiling module lpm_counter
# -- Compiling module lpm_latch
# -- Compiling module lpm_ff
# -- Compiling module lpm_shiftreg
# -- Compiling module lpm_ram_dq
# -- Compiling module lpm_ram_dp
# -- Compiling module lpm_ram_io
# -- Compiling module lpm_rom
# -- Compiling module lpm_fifo
# -- Compiling module lpm_fifo_dc_dffpipe
# -- Compiling module lpm_fifo_dc_fefifo
# -- Compiling module lpm_fifo_dc_async
# -- Compiling module lpm_fifo_dc
# -- Compiling module lpm_inpad
# -- Compiling module lpm_outpad
# -- Compiling module lpm_bipad
# 
# Top level modules:
# 	lpm_constant
# 	lpm_inv
# 	lpm_and
# 	lpm_or
# 	lpm_xor
# 	lpm_bustri
# 	lpm_mux
# 	lpm_decode
# 	lpm_clshift
# 	lpm_add_sub
# 	lpm_compare
# 	lpm_mult
# 	lpm_divide
# 	lpm_abs
# 	lpm_counter
# 	lpm_latch
# 	lpm_ff
# 	lpm_shiftreg
# 	lpm_ram_dq
# 	lpm_ram_dp
# 	lpm_ram_io
# 	lpm_rom
# 	lpm_fifo
# 	lpm_fifo_dc
# 	lpm_inpad
# 	lpm_outpad
# 	lpm_bipad
# End time: 09:28:04 on May 08,2024, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# 
# vlib verilog_libs/sgate_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/sgate_ver".
# vmap sgate_ver ./verilog_libs/sgate_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap sgate_ver ./verilog_libs/sgate_ver 
# Modifying modelsim.ini
# vlog -vlog01compat -work sgate_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/sgate.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:04 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work sgate_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/sgate.v 
# -- Compiling module oper_add
# -- Compiling module oper_addsub
# -- Compiling module mux21
# -- Compiling module io_buf_tri
# -- Compiling module io_buf_opdrn
# -- Compiling module oper_mult
# -- Compiling module tri_bus
# -- Compiling module oper_div
# -- Compiling module oper_mod
# -- Compiling module oper_left_shift
# -- Compiling module oper_right_shift
# -- Compiling module oper_rotate_left
# -- Compiling module oper_rotate_right
# -- Compiling module oper_less_than
# -- Compiling module oper_mux
# -- Compiling module oper_selector
# -- Compiling module oper_decoder
# -- Compiling module oper_bus_mux
# -- Compiling module oper_latch
# 
# Top level modules:
# 	oper_add
# 	oper_addsub
# 	mux21
# 	io_buf_tri
# 	io_buf_opdrn
# 	oper_mult
# 	tri_bus
# 	oper_div
# 	oper_mod
# 	oper_left_shift
# 	oper_right_shift
# 	oper_rotate_left
# 	oper_rotate_right
# 	oper_less_than
# 	oper_mux
# 	oper_selector
# 	oper_decoder
# 	oper_bus_mux
# 	oper_latch
# End time: 09:28:04 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlib verilog_libs/altera_mf_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_mf_ver".
# vmap altera_mf_ver ./verilog_libs/altera_mf_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap altera_mf_ver ./verilog_libs/altera_mf_ver 
# Modifying modelsim.ini
# vlog -vlog01compat -work altera_mf_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/altera_mf.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:04 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work altera_mf_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/altera_mf.v 
# -- Compiling module lcell
# -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
# -- Compiling module ALTERA_MF_HINT_EVALUATION
# -- Compiling module ALTERA_DEVICE_FAMILIES
# -- Compiling module dffp
# -- Compiling module pll_iobuf
# -- Compiling module stx_m_cntr
# -- Compiling module stx_n_cntr
# -- Compiling module stx_scale_cntr
# -- Compiling module MF_pll_reg
# -- Compiling module MF_stratix_pll
# -- Compiling module arm_m_cntr
# -- Compiling module arm_n_cntr
# -- Compiling module arm_scale_cntr
# -- Compiling module MF_stratixii_pll
# -- Compiling module ttn_m_cntr
# -- Compiling module ttn_n_cntr
# -- Compiling module ttn_scale_cntr
# -- Compiling module MF_stratixiii_pll
# -- Compiling module cda_m_cntr
# -- Compiling module cda_n_cntr
# -- Compiling module cda_scale_cntr
# -- Compiling module MF_cycloneiii_pll
# -- Compiling module MF_cycloneiiigl_m_cntr
# -- Compiling module MF_cycloneiiigl_n_cntr
# -- Compiling module MF_cycloneiiigl_scale_cntr
# -- Compiling module cycloneiiigl_post_divider
# -- Compiling module MF_cycloneiiigl_pll
# -- Compiling module altpll
# -- Compiling module altlvds_rx
# -- Compiling module stratix_lvds_rx
# -- Compiling module stratixgx_dpa_lvds_rx
# -- Compiling module stratixii_lvds_rx
# -- Compiling module flexible_lvds_rx
# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel
# -- Compiling module stratixiii_lvds_rx_dpa
# -- Compiling module altlvds_tx
# -- Compiling module stratixv_local_clk_divider
# -- Compiling module stratix_tx_outclk
# -- Compiling module stratixii_tx_outclk
# -- Compiling module flexible_lvds_tx
# -- Compiling module dcfifo_dffpipe
# -- Compiling module dcfifo_fefifo
# -- Compiling module dcfifo_async
# -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency
# -- Compiling module dcfifo_mixed_widths
# -- Compiling module dcfifo
# -- Compiling module altera_syncram_derived
# -- Compiling module altera_syncram_derived_forwarding_logic
# -- Compiling module altaccumulate
# -- Compiling module altmult_accum
# -- Compiling module altmult_add
# -- Compiling module altfp_mult
# -- Compiling module altsqrt
# -- Compiling module altclklock
# -- Compiling module altddio_in
# -- Compiling module altddio_out
# -- Compiling module altddio_bidir
# -- Compiling module altdpram
# -- Compiling module altsyncram
# -- Compiling module altsyncram_body
# -- Compiling module alt3pram
# -- Compiling module parallel_add
# -- Compiling module scfifo
# -- Compiling module altshift_taps
# -- Compiling module a_graycounter
# -- Compiling module altsquare
# -- Compiling module altera_std_synchronizer
# -- Compiling module altera_std_synchronizer_bundle
# -- Compiling module alt_cal
# -- Compiling module alt_cal_mm
# -- Compiling module alt_cal_c3gxb
# -- Compiling module alt_cal_sv
# -- Compiling module alt_cal_av
# -- Compiling module alt_aeq_s4
# -- Compiling module alt_eyemon
# -- Compiling module alt_dfe
# -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller
# -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag
# -- Compiling module sld_signaltap
# -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader
# -- Compiling module altserial_flash_loader
# -- Compiling module alt_fault_injection
# -- Compiling module sld_virtual_jtag_basic
# -- Compiling module altsource_probe
# 
# Top level modules:
# 	lcell
# 	altpll
# 	altlvds_rx
# 	altlvds_tx
# 	dcfifo
# 	altaccumulate
# 	altmult_accum
# 	altmult_add
# 	altfp_mult
# 	altsqrt
# 	altclklock
# 	altddio_bidir
# 	altdpram
# 	alt3pram
# 	parallel_add
# 	scfifo
# 	altshift_taps
# 	a_graycounter
# 	altsquare
# 	altera_std_synchronizer_bundle
# 	alt_cal
# 	alt_cal_mm
# 	alt_cal_c3gxb
# 	alt_cal_sv
# 	alt_cal_av
# 	alt_aeq_s4
# 	alt_eyemon
# 	alt_dfe
# 	sld_virtual_jtag
# 	sld_signaltap
# 	altstratixii_oct
# 	altparallel_flash_loader
# 	altserial_flash_loader
# 	alt_fault_injection
# 	sld_virtual_jtag_basic
# 	altsource_probe
# End time: 09:28:05 on May 08,2024, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# 
# vlib verilog_libs/altera_lnsim_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_lnsim_ver".
# vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver 
# Modifying modelsim.ini
# vlog -sv -work altera_lnsim_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/altera_lnsim.sv}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:06 on May 08,2024
# vlog -reportprogress 300 -sv -work altera_lnsim_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/altera_lnsim.sv 
# -- Compiling package altera_lnsim_functions
# -- Compiling package altera_generic_pll_functions
# -- Compiling module generic_pll
# -- Importing package altera_lnsim_functions
# -- Importing package altera_generic_pll_functions
# -- Compiling module generic_cdr
# -- Compiling module common_28nm_ram_pulse_generator
# -- Compiling module common_28nm_ram_register
# -- Compiling module common_28nm_ram_block
# -- Compiling module generic_m20k
# -- Compiling module generic_m10k
# -- Compiling module common_28nm_mlab_cell_pulse_generator
# -- Compiling module common_28nm_mlab_latch
# -- Compiling module common_28nm_mlab_cell_core
# -- Compiling module common_porta_latches
# -- Compiling module generic_28nm_hp_mlab_cell_impl
# -- Compiling module common_porta_registers
# -- Compiling module generic_28nm_lc_mlab_cell_impl
# -- Compiling module common_28nm_lutram_register
# -- Compiling module generic_14nm_mlab_cell_impl
# -- Compiling module common_14nm_lutram_register
# -- Compiling module generic_mux
# -- Compiling module generic_device_pll
# -- Compiling module altera_mult_add
# -- Compiling module altera_mult_add_rtl
# -- Compiling module ama_signed_extension_function
# -- Compiling module ama_dynamic_signed_function
# -- Compiling module ama_register_function
# -- Compiling module ama_register_with_ext_function
# -- Compiling module ama_data_split_reg_ext_function
# -- Compiling module ama_coef_reg_ext_function
# -- Compiling module ama_adder_function
# -- Compiling module ama_multiplier_function
# -- Compiling module ama_preadder_function
# -- Compiling module ama_chainout_adder_accumulator_function
# -- Compiling module ama_systolic_adder_function
# -- Compiling module ama_scanchain
# -- Compiling module ama_latency_function
# -- Compiling module altera_pll_reconfig_tasks
# -- Compiling module altera_syncram
# -- Compiling module altera_syncram_forwarding_logic
# -- Compiling module ALTERA_LNSIM_MEMORY_INITIALIZATION
# -- Compiling module altera_stratixv_pll
# -- Compiling module altera_arriav_pll
# -- Compiling module altera_arriavgz_pll
# -- Compiling module altera_cyclonev_pll
# -- Compiling module altera_pll
# -- Compiling module dps_extra_kick
# -- Compiling module dprio_init
# -- Compiling module dps_pulse_gen
# -- Compiling module altera_iopll
# -- Compiling module dps_pulse_gen_iopll
# -- Compiling module twentynm_iopll_arlol
# -- Compiling module fourteennm_altera_iopll
# -- Compiling module dps_pulse_gen_fourteennm_iopll
# -- Compiling package fourteennm_iopll_functions
# -- Compiling module fourteennm_simple_iopll
# -- Importing package fourteennm_iopll_functions
# -- Compiling module fourteennm_sub_iopll
# -- Compiling module twentynm_iopll_ip
# -- Compiling module altera_iopll_rotation_lcells
# -- Compiling module altera_pll_dps_lcell_comb
# -- Compiling module iopll_bootstrap
# 
# Top level modules:
# 	generic_cdr
# 	generic_m20k
# 	generic_m10k
# 	common_porta_latches
# 	generic_28nm_hp_mlab_cell_impl
# 	generic_28nm_lc_mlab_cell_impl
# 	generic_14nm_mlab_cell_impl
# 	generic_mux
# 	generic_device_pll
# 	altera_mult_add
# 	altera_pll_reconfig_tasks
# 	altera_syncram
# 	altera_pll
# 	altera_iopll
# 	fourteennm_altera_iopll
# 	fourteennm_simple_iopll
# End time: 09:28:06 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlib verilog_libs/cyclonev_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/cyclonev_ver".
# vmap cyclonev_ver ./verilog_libs/cyclonev_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap cyclonev_ver ./verilog_libs/cyclonev_ver 
# Modifying modelsim.ini
# vlog -vlog01compat -work cyclonev_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:06 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work cyclonev_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v 
# 
# Top level modules:
# End time: 09:28:08 on May 08,2024, Elapsed time: 0:00:02
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work cyclonev_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:08 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work cyclonev_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v 
# 
# Top level modules:
# End time: 09:28:10 on May 08,2024, Elapsed time: 0:00:02
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work cyclonev_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/cyclonev_atoms.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:10 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work cyclonev_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/cyclonev_atoms.v 
# -- Compiling UDP CYCLONEV_PRIM_DFFE
# -- Compiling UDP CYCLONEV_PRIM_DFFEAS
# -- Compiling UDP CYCLONEV_PRIM_DFFEAS_HIGH
# -- Compiling module cyclonev_dffe
# -- Compiling module cyclonev_mux21
# -- Compiling module cyclonev_mux41
# -- Compiling module cyclonev_and1
# -- Compiling module cyclonev_and16
# -- Compiling module cyclonev_bmux21
# -- Compiling module cyclonev_b17mux21
# -- Compiling module cyclonev_nmux21
# -- Compiling module cyclonev_b5mux21
# -- Compiling module cyclonev_ff
# -- Compiling module cyclonev_lcell_comb
# -- Compiling module cyclonev_routing_wire
# -- Compiling module cyclonev_ram_block
# -- Compiling module cyclonev_mlab_cell
# -- Compiling module cyclonev_io_ibuf
# -- Compiling module cyclonev_io_obuf
# -- Compiling module cyclonev_ddio_out
# -- Compiling module cyclonev_ddio_oe
# -- Compiling module cyclonev_ddio_in
# -- Compiling module cyclonev_io_pad
# -- Compiling module cyclonev_pseudo_diff_out
# -- Compiling module cyclonev_bias_logic
# -- Compiling module cyclonev_bias_generator
# -- Compiling module cyclonev_bias_block
# -- Compiling module cyclonev_clk_phase_select
# -- Compiling module cyclonev_clkena
# -- Compiling module cyclonev_clkselect
# -- Compiling module cyclonev_delay_chain
# -- Compiling module cyclonev_dll_offset_ctrl
# -- Compiling module cyclonev_dll
# -- Compiling module cyclonev_dqs_config
# -- Compiling module cyclonev_dqs_delay_chain
# -- Compiling module cyclonev_dqs_enable_ctrl
# -- Compiling module cyclonev_duty_cycle_adjustment
# -- Compiling module cyclonev_fractional_pll
# -- Compiling module cyclonev_half_rate_input
# -- Compiling module cyclonev_input_phase_alignment
# -- Compiling module cyclonev_io_clock_divider
# -- Compiling module cyclonev_io_config
# -- Compiling module cyclonev_leveling_delay_chain
# -- Compiling module cyclonev_pll_dll_output
# -- Compiling module cyclonev_pll_dpa_output
# -- Compiling module cyclonev_pll_extclk_output
# -- Compiling module cyclonev_pll_lvds_output
# -- Compiling module cyclonev_pll_output_counter
# -- Compiling module cyclonev_pll_reconfig
# -- Compiling module cyclonev_pll_refclk_select
# -- Compiling module cyclonev_termination_logic
# -- Compiling module cyclonev_termination
# -- Compiling module cyclonev_asmiblock
# -- Compiling module cyclonev_chipidblock
# -- Compiling module cyclonev_controller
# -- Compiling module cyclonev_crcblock
# -- Compiling module cyclonev_jtag
# -- Compiling module cyclonev_prblock
# -- Compiling module cyclonev_rublock
# -- Compiling module cyclonev_tsdblock
# -- Compiling module cyclonev_read_fifo
# -- Compiling module cyclonev_read_fifo_read_enable
# -- Compiling module cyclonev_phy_clkbuf
# -- Compiling module cyclonev_ir_fifo_userdes
# -- Compiling module cyclonev_read_fifo_read_clock_select
# -- Compiling module cyclonev_lfifo
# -- Compiling module cyclonev_vfifo
# -- Compiling module cyclonev_mac
# -- Compiling module cyclonev_mem_phy
# -- Compiling module cyclonev_oscillator
# -- Compiling module cyclonev_hps_interface_fpga2sdram
# 
# Top level modules:
# 	cyclonev_dffe
# 	cyclonev_mux41
# 	cyclonev_and1
# 	cyclonev_and16
# 	cyclonev_bmux21
# 	cyclonev_b17mux21
# 	cyclonev_nmux21
# 	cyclonev_b5mux21
# 	cyclonev_ff
# 	cyclonev_lcell_comb
# 	cyclonev_routing_wire
# 	cyclonev_ram_block
# 	cyclonev_mlab_cell
# 	cyclonev_io_ibuf
# 	cyclonev_io_obuf
# 	cyclonev_ddio_out
# 	cyclonev_ddio_oe
# 	cyclonev_ddio_in
# 	cyclonev_io_pad
# 	cyclonev_pseudo_diff_out
# 	cyclonev_bias_block
# 	cyclonev_clk_phase_select
# 	cyclonev_clkena
# 	cyclonev_clkselect
# 	cyclonev_delay_chain
# 	cyclonev_dll_offset_ctrl
# 	cyclonev_dll
# 	cyclonev_dqs_config
# 	cyclonev_dqs_delay_chain
# 	cyclonev_dqs_enable_ctrl
# 	cyclonev_duty_cycle_adjustment
# 	cyclonev_fractional_pll
# 	cyclonev_half_rate_input
# 	cyclonev_input_phase_alignment
# 	cyclonev_io_clock_divider
# 	cyclonev_io_config
# 	cyclonev_leveling_delay_chain
# 	cyclonev_pll_dll_output
# 	cyclonev_pll_dpa_output
# 	cyclonev_pll_extclk_output
# 	cyclonev_pll_lvds_output
# 	cyclonev_pll_output_counter
# 	cyclonev_pll_reconfig
# 	cyclonev_pll_refclk_select
# 	cyclonev_termination_logic
# 	cyclonev_termination
# 	cyclonev_asmiblock
# 	cyclonev_chipidblock
# 	cyclonev_controller
# 	cyclonev_crcblock
# 	cyclonev_jtag
# 	cyclonev_prblock
# 	cyclonev_rublock
# 	cyclonev_tsdblock
# 	cyclonev_read_fifo
# 	cyclonev_read_fifo_read_enable
# 	cyclonev_phy_clkbuf
# 	cyclonev_ir_fifo_userdes
# 	cyclonev_read_fifo_read_clock_select
# 	cyclonev_lfifo
# 	cyclonev_vfifo
# 	cyclonev_mac
# 	cyclonev_mem_phy
# 	cyclonev_oscillator
# 	cyclonev_hps_interface_fpga2sdram
# End time: 09:28:10 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlib verilog_libs/cyclonev_hssi_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/cyclonev_hssi_ver".
# vmap cyclonev_hssi_ver ./verilog_libs/cyclonev_hssi_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap cyclonev_hssi_ver ./verilog_libs/cyclonev_hssi_ver 
# Modifying modelsim.ini
# vlog -vlog01compat -work cyclonev_hssi_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:10 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work cyclonev_hssi_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v 
# 
# Top level modules:
# End time: 09:28:12 on May 08,2024, Elapsed time: 0:00:02
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work cyclonev_hssi_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/cyclonev_hssi_atoms.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:12 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work cyclonev_hssi_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/cyclonev_hssi_atoms.v 
# -- Compiling module cyclonev_hssi_8g_pcs_aggregate
# -- Compiling module cyclonev_hssi_8g_rx_pcs
# -- Compiling module cyclonev_hssi_8g_tx_pcs
# -- Compiling module cyclonev_hssi_common_pcs_pma_interface
# -- Compiling module cyclonev_hssi_common_pld_pcs_interface
# -- Compiling module cyclonev_hssi_pipe_gen1_2
# -- Compiling module cyclonev_hssi_pma_aux
# -- Compiling module cyclonev_hssi_pma_int
# -- Compiling module cyclonev_hssi_pma_rx_buf
# -- Compiling module cyclonev_hssi_pma_rx_deser
# -- Compiling module cyclonev_hssi_pma_tx_buf
# -- Compiling module cyclonev_hssi_pma_tx_cgb
# -- Compiling module cyclonev_hssi_pma_tx_ser
# -- Compiling module cyclonev_hssi_pma_cdr_refclk_select_mux
# -- Compiling module cyclonev_hssi_rx_pcs_pma_interface
# -- Compiling module cyclonev_hssi_rx_pld_pcs_interface
# -- Compiling module cyclonev_hssi_tx_pcs_pma_interface
# -- Compiling module cyclonev_hssi_tx_pld_pcs_interface
# -- Compiling module cyclonev_hssi_refclk_divider
# -- Compiling module cyclonev_pll_aux
# -- Compiling module cyclonev_channel_pll
# -- Compiling module cyclonev_hssi_avmm_interface
# -- Compiling module cyclonev_hssi_pma_hi_pmaif
# -- Compiling module cyclonev_hssi_pma_hi_xcvrif
# -- Compiling module arriav_hssi_8g_pcs_aggregate
# -- Compiling module arriav_hssi_8g_rx_pcs
# -- Compiling module arriav_hssi_8g_tx_pcs
# -- Compiling module arriav_hssi_common_pcs_pma_interface
# -- Compiling module arriav_hssi_common_pld_pcs_interface
# -- Compiling module arriav_hssi_pipe_gen1_2
# -- Compiling module arriav_hssi_pma_aux
# -- Compiling module arriav_hssi_pma_int
# -- Compiling module arriav_hssi_pma_rx_buf
# -- Compiling module arriav_hssi_pma_rx_deser
# -- Compiling module arriav_hssi_pma_tx_buf
# -- Compiling module arriav_hssi_pma_tx_cgb
# -- Compiling module arriav_hssi_pma_tx_ser
# -- Compiling module arriav_hssi_pma_cdr_refclk_select_mux
# -- Compiling module arriav_hssi_rx_pcs_pma_interface
# -- Compiling module arriav_hssi_rx_pld_pcs_interface
# -- Compiling module arriav_hssi_tx_pcs_pma_interface
# -- Compiling module arriav_hssi_tx_pld_pcs_interface
# -- Compiling module arriav_hssi_refclk_divider
# -- Compiling module arriav_pll_aux
# -- Compiling module arriav_channel_pll
# -- Compiling module arriav_hssi_avmm_interface
# -- Compiling module arriav_hssi_pma_hi_pmaif
# -- Compiling module arriav_hssi_pma_hi_xcvrif
# 
# Top level modules:
# 	cyclonev_hssi_8g_pcs_aggregate
# 	cyclonev_hssi_8g_rx_pcs
# 	cyclonev_hssi_8g_tx_pcs
# 	cyclonev_hssi_common_pcs_pma_interface
# 	cyclonev_hssi_common_pld_pcs_interface
# 	cyclonev_hssi_pipe_gen1_2
# 	cyclonev_hssi_pma_aux
# 	cyclonev_hssi_pma_int
# 	cyclonev_hssi_pma_rx_buf
# 	cyclonev_hssi_pma_rx_deser
# 	cyclonev_hssi_pma_tx_buf
# 	cyclonev_hssi_pma_tx_cgb
# 	cyclonev_hssi_pma_tx_ser
# 	cyclonev_hssi_pma_cdr_refclk_select_mux
# 	cyclonev_hssi_rx_pcs_pma_interface
# 	cyclonev_hssi_rx_pld_pcs_interface
# 	cyclonev_hssi_tx_pcs_pma_interface
# 	cyclonev_hssi_tx_pld_pcs_interface
# 	cyclonev_hssi_refclk_divider
# 	cyclonev_pll_aux
# 	cyclonev_channel_pll
# 	cyclonev_hssi_avmm_interface
# 	cyclonev_hssi_pma_hi_pmaif
# 	cyclonev_hssi_pma_hi_xcvrif
# 	arriav_hssi_8g_pcs_aggregate
# 	arriav_hssi_8g_rx_pcs
# 	arriav_hssi_8g_tx_pcs
# 	arriav_hssi_common_pcs_pma_interface
# 	arriav_hssi_common_pld_pcs_interface
# 	arriav_hssi_pipe_gen1_2
# 	arriav_hssi_pma_aux
# 	arriav_hssi_pma_int
# 	arriav_hssi_pma_rx_buf
# 	arriav_hssi_pma_rx_deser
# 	arriav_hssi_pma_tx_buf
# 	arriav_hssi_pma_tx_cgb
# 	arriav_hssi_pma_tx_ser
# 	arriav_hssi_pma_cdr_refclk_select_mux
# 	arriav_hssi_rx_pcs_pma_interface
# 	arriav_hssi_rx_pld_pcs_interface
# 	arriav_hssi_tx_pcs_pma_interface
# 	arriav_hssi_tx_pld_pcs_interface
# 	arriav_hssi_refclk_divider
# 	arriav_pll_aux
# 	arriav_channel_pll
# 	arriav_hssi_avmm_interface
# 	arriav_hssi_pma_hi_pmaif
# 	arriav_hssi_pma_hi_xcvrif
# End time: 09:28:12 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlib verilog_libs/cyclonev_pcie_hip_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/cyclonev_pcie_hip_ver".
# vmap cyclonev_pcie_hip_ver ./verilog_libs/cyclonev_pcie_hip_ver
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap cyclonev_pcie_hip_ver ./verilog_libs/cyclonev_pcie_hip_ver 
# Modifying modelsim.ini
# vlog -vlog01compat -work cyclonev_pcie_hip_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:12 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work cyclonev_pcie_hip_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v 
# 
# Top level modules:
# End time: 09:28:15 on May 08,2024, Elapsed time: 0:00:03
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work cyclonev_pcie_hip_ver {/tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/cyclonev_pcie_hip_atoms.v}
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:15 on May 08,2024
# vlog -reportprogress 300 -vlog01compat -work cyclonev_pcie_hip_ver /tools/intel/intelFPGA/21.1/quartus/eda/sim_lib/cyclonev_pcie_hip_atoms.v 
# -- Compiling module cyclonev_hd_altpe2_hip_top
# -- Compiling module arriav_hd_altpe2_hip_top
# 
# Top level modules:
# 	cyclonev_hd_altpe2_hip_top
# End time: 09:28:15 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap work rtl_work 
# Modifying modelsim.ini
# 
###### Libraries for IPUTF cores 
# vlib fft_sim_iputf_libs/nco_ii_0
# ** Warning: (vlib-34) Library already exists at "fft_sim_iputf_libs/nco_ii_0".
# vmap nco_ii_0 ./fft_sim_iputf_libs/nco_ii_0
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap nco_ii_0 ./fft_sim_iputf_libs/nco_ii_0 
# Modifying modelsim.ini
# vlib fft_sim_iputf_libs/fft_ii_0
# ** Warning: (vlib-34) Library already exists at "fft_sim_iputf_libs/fft_ii_0".
# vmap fft_ii_0 ./fft_sim_iputf_libs/fft_ii_0
# QuestaSim vmap 10.7b_1 Lib Mapping Utility 2018.07 Jul 26 2018
# vmap fft_ii_0 ./fft_sim_iputf_libs/fft_ii_0 
# Modifying modelsim.ini
###### End libraries for IPUTF cores 
###### MIF file copy and HDL compilation commands for IPUTF cores 
# 
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/nco_nco_ii_0_sin.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/nco_nco_ii_0_cos.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twi5.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twi1.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twr4.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twr5.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twr1.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twi2.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twi3.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twr2.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twi4.hex ./
# file copy -force /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/fft_fft_ii_0_opt_twr3.hex ./
# 
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_mob_rw.v"                              -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:16 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_mob_rw.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:16 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_isdr.v"                                -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:16 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_isdr.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:16 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_apr_dxx.v"                             -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:16 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_apr_dxx.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:16 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_dxx_g.v"                                   -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:16 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_dxx_g.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:17 on May 08,2024, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_dxx.v"                                     -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:17 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_dxx.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:17 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_gal.v"                                     -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:17 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_gal.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:17 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_as_m_cen.v"                            -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:17 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_nco_as_m_cen.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:17 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_altqmcpipe.v"                              -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:17 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/mentor/asj_altqmcpipe.v -work nco_ii_0 
# 
# Top level modules:
# End time: 09:28:17 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/nco_nco_ii_0.v"                                       -work nco_ii_0
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:17 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/submodules/nco_nco_ii_0.v -work nco_ii_0 
# -- Compiling module nco_nco_ii_0
# 
# Top level modules:
# 	nco_nco_ii_0
# End time: 09:28:17 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/nco.v"                                                                         
# QuestaSim vlog 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:17 on May 08,2024
# vlog -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/nco/simulation/nco.v 
# -- Compiling module nco
# 
# Top level modules:
# 	nco
# End time: 09:28:17 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/auk_dspip_text_pkg.vhd"                               -work fft_ii_0
# QuestaSim vcom 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:18 on May 08,2024
# vcom -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/auk_dspip_text_pkg.vhd -work fft_ii_0 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling package auk_dspip_text_pkg
# -- Compiling package body auk_dspip_text_pkg
# -- Loading package auk_dspip_text_pkg
# End time: 09:28:18 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/auk_dspip_math_pkg.vhd"                               -work fft_ii_0
# QuestaSim vcom 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:18 on May 08,2024
# vcom -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/auk_dspip_math_pkg.vhd -work fft_ii_0 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling package auk_dspip_math_pkg
# -- Compiling package body auk_dspip_math_pkg
# -- Loading package auk_dspip_math_pkg
# End time: 09:28:18 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/auk_dspip_lib_pkg.vhd"                                -work fft_ii_0
# QuestaSim vcom 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:18 on May 08,2024
# vcom -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/auk_dspip_lib_pkg.vhd -work fft_ii_0 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package auk_dspip_math_pkg
# -- Compiling package auk_dspip_lib_pkg
# End time: 09:28:18 on May 08,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd"     -work fft_ii_0
# QuestaSim vcom 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:18 on May 08,2024
# vcom -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd -work fft_ii_0 
# -- Loading package STANDARD
# End time: 09:28:19 on May 08,2024, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd"   -work fft_ii_0
# QuestaSim vcom 10.7b_1 Compiler 2018.07 Jul 26 2018
# Start time: 09:28:19 on May 08,2024
# vcom -reportprogress 300 /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd -work fft_ii_0 
# -- Loading package STANDARD
# ** Error: /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd(38): (vcom-1598) Library "altera_mf" not found.
# ** Error: /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd(38): (vcom-1136) Unknown identifier "<protected>".
# ** Note: /homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd(38): VHDL Compiler exiting
# End time: 09:28:19 on May 08,2024, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# ** Error: /tools/mentor/questa_10.7b_1/questasim/linux/vcom failed.
# Error in macro ./fft_sim_run_msim_rtl_verilog.do line 87
# /tools/mentor/questa_10.7b_1/questasim/linux/vcom failed.
#     while executing
# "vcom     "/homes/user/stud/fall21/mhr2154/Documents/fft_sim/fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd"   -work fft_..."
